1. Field of the Invention
The present invention relates to a semiconductor device having a memory cell region in which at least a field-effect transistor is formed and a non-memory cell region in which at least a bipolar transistor is formed, and a method of fabricating the same.
2. Description of the Related Art
An SRAM has a memory cell region and a peripheral circuit region. FIG. 18 shows an equivalent circuit of a memory cell of a high-resistance load type SRAM. A flip-flop 11 of this memory cell includes NMOS transistors 12 and 13 for driving and resistive elements 14 and 15 as loads. The memory cell is constituted by this flip-flop 11 and transfer NMOS transistors 16 and 17.
A ground line 21 is connected to the source regions of the NMOS transistors 12 and 13, and a power line 22 is connected to the resistive elements 14 and 15. Also, a word line 23 serves as a gate electrode of the NMOS transistors 16 and 17. A pair of non-inverted and inverted bit lines 24 and 25 are each connected to one of the source/drain regions of the NMOS transistors 16 and 17, respectively.
In an SRAM with this arrangement, the drain regions of the NMOS transistors 12 and 13 serve as storage node diffusion layers. Electric charge is stored in these drain regions, and data is stored by setting these drain regions at a predetermined potential. However, if .alpha. rays emitted from a slight amount of a radioactive element such as uranium or thorium contained in a packaging mold resin or the like enter a semiconductor base, electron-hole pairs are generated by impact ionization by the .alpha. rays.
Holes of the generated electron-hole pairs flow in a grounded P-well in the semiconductor base. Electrons are trapped in the drain regions of the NMOS transistors 12 and 13 and the like to which a positive voltage is applied. As a consequence, the amount of electric charge stored in these drain regions varies, and this can cause a soft error in which the potential of these drain regions is inverted to invert the stored data.
Especially when .alpha. rays penetrate through the drain regions and their depletion layers of the NMOS transistors 12 and 13, these depletion layers instantaneously extend to bring about a funneling phenomenon. Consequently, the electron trap efficiency increases, and this can further increase the possibility of a soft error.
It is, therefore, being attempted to add a capacitor between the storage nodes to trap electrons generated by the impact ionization into this capacitor (e.g., Japanese Patent Laid-Open No. 62-154296), or to form a P.sup.+ -type buried diffusion layer, as a potential barrier against electrons, in a memory cell region to thereby prevent diffused electrons from moving into the depletion layers (e.g., Japanese Patent Laid-Open No. 62-245660).
A bipolar transistor is formed in a peripheral circuit region or the like of an SRAM. As is well known, when the base and emitter regions of a bipolar transistor are formed by rapid thermal annealing such as halogen lamp annealing, the base width which is the difference between the depths of the base and emitter regions can be accurately controlled, and consequently the characteristics of the bipolar transistor, particularly the high-frequency characteristics such as the cut-off frequency can be improved.
The structure in which a capacitor is additionally formed as described in Japanese Patent Laid-Open No. 62-154296 is effective to a semiconductor device, such as a TFT load type SRAM, using two conductive layers as load elements. However, it is difficult to apply this structure to a semiconductor device, such as a high-resistance load type SRAM, using only one conductive layer as a load element, since a capacitor is difficult to form.
In the case of the structure in which a P.sup.+ -type buried diffusion layer is formed in a memory cell region as described in Japanese Patent Laid-Open No. 62-245660, it is necessary to add fabrication steps of additionally forming this P.sup.+ -type buried diffusion layer. Therefore, it is difficult to increase the soft error resistance while suppressing an increase in the fabrication cost.
In addition, when the P.sup.+ -type buried diffusion layer is formed by high-energy ion implantation, defective layers may locally remain in a semiconductor base due to ion implantation damage even if annealing for recovering the crystallinity is performed after the ion implantation. Accordingly, it is difficult to increase the soft error resistance without lowering the storage retention ability on a one-bit level.
Furthermore, when the base and emitter regions are formed by rapid thermal annealing in order to improve the characteristics of a bipolar transistor in a peripheral circuit region of an SRAM or the like, an impurity in load elements such as the resistive elements 14 and 15 diffuses, and the characteristics of the load elements vary. Also, a gate insulating film deteriorates, and hot carriers are injected into the gate insulating film. Consequently, the characteristics such as the gate withstand voltage and the life of a MOS transistor in a memory cell region or the like easily deteriorate.
As described above, a large number of conventional methods have been reported which apply rapid thermal annealing to a simple device including only a bipolar transistor to improve its characteristics. However, it is conventionally difficult, by applying rapid thermal annealing to a composite device such as an SRAM having a bipolar transistor in a peripheral circuit region, to fabricate a semiconductor device in which elements such as a load element and a MOS transistor, other than the bipolar transistor, also have excellent characteristics.